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LTC3545/LTC3545-1 Triple 800mA Synchronous Step-Down Regulator-2.25MHz FEATURES

DESCRIPTION
The LTC (R)3545/LTC3545-1 are triple, high efficiency, monolithic synchronous buck regulators using a constant frequency, current mode architecture. The regulators operate independently with separate run pins. The 2.25V to 5.5V input voltage range makes the LTC3545/LTC3545-1 well suited for single Li-Ion battery-powered applications. Low ripple pulse skip mode or high efficiency Burst Mode operation is externally selectable. PWM pulse skip mode operation provides very low output ripple voltage while Burst Mode operation increases efficiency at low output loads. Switching frequency is internally set to 2.25MHz, or the switching frequency can be synchronized to an external 1MHz to 3MHz clock. Power good indicators easily allow power on sequencing between the three regulators. The internal synchronous switches increase efficiency and eliminate external Schottky diodes. Low output voltages are supported with the 0.6V feedback reference voltage. The LTC3545-1 replaces the SYNC/MODE function with a third PGOOD pin and forces Burst Mode operation.

Three 800mA Outputs High Efficiency: Up to 95% 2.25V to 5.5V Input Voltage Range Low Ripple (<20mVP-P) Burst Mode(R) Operation IQ: 58A 2.25MHz Constant Frequency Operation or Synchronizable to External 1MHz to 3MHz Clock Power Good Indicators Ease Supply Sequencing 0.6V Reference Allows Low Output Voltages Current Mode Operation/Excellent Transient Response Low Profile 16-Lead 3mm x 3mm QFN Package
APPLICATIONS

Smart Phones Wireless and DSL Modems Digital Still Cameras Portable Instruments Point of Load Regulation
L, LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 6580258, 5481178, 6127815, 6498466, 6611131.
TYPICAL APPLICATION
High Efficiency Triple Step-Down Converter with Power Sequencing
VIN 2.25V TO 5.5V C4 10F GNDA R8 500k R7 500k RUN1 PGOOD1 RUN2 PGOOD2 RUN3 L1 1.5H C6 20pF LTC3545 L3 1.5H SW3 C8 20pF VFB2 R4 226k R3 226k C2 10F VIN PVIN C5 10F PGND L2 1.5H C7 20pF
Efficiency and Loss vs Load Current
100 90 80 EFFICIENCY (%) VOUT2 1.2V 70 60 50 40 30 20 10 VOUT3 1.5V C3 10F R5 301k
3545 TA01
1
0.1 LOSS (W)
SW2
0.01
0.001 VIN = 2.5V VIN = 3.6V VIN = 4.2V 0.01 0.1 0.001 LOAD CURRENT (A) 1
3545 TA01b
SYNC/MODE SW1
VOUT1 1.8V C1 10F
0 0.0001
0.0001
VFB1 R1 511k R2 255k GNDA PGND
VFB3 R6 200k
TA = 25C VOUT = 2V Burst Mode OPERATION fOSC = 2.25MHz SINGLE CHANNEL
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LTC3545/LTC3545-1 ABSOLUTE MAXIMUM RATINGS
(Note 1)
Input Supply Voltage .................................... -0.3V to 6V RUNx, PGOODx............................. -0.3V to (VIN + 0.3V) VFBx, SYNC/MODE ........................ -0.3V to (VIN + 0.3V) SWx .............................................. -0.3V to (VIN + 0.3V) P-Switch Source Current (DC) (Note 8) ...................1.1A
N-Channel Sink Current (DC) (Note 8) .....................1.1A Peak SW Sink and Source Current (Note 8) .............1.3A Operating Junction Temperature Range (Note 2) ............................................. -40C to 125C Storage Temperature Range................... -65C to 125C
PIN CONFIGURATION
LTC3545 TOP VIEW GNDA RUN1 VFB1 VIN LTC3545-1 TOP VIEW GNDA RUN1 VFB1 12 VFB2 17 11 VFB3 10 RUN3 9 5 SW2 6 PGND 7 PVIN 8 SW3 PGOOD3 VIN
16 15 14 13 SW1 1 PGOOD1 2 RUN2 3 PGOOD2 4 5 SW2 6 PGND 7 PVIN 8 SW3 17 12 VFB2 11 VFB3 10 RUN3 9 SYNC/MODE SW1 1 PGOOD1 2 RUN2 3 PGOOD2 4
16 15 14 13
UD PACKAGE 16-LEAD (3mm 3mm) PLASTIC QFN TJMAX = 125C, JA = 55C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
UD PACKAGE 16-LEAD (3mm 3mm) PLASTIC QFN TJMAX = 125C, JA = 55C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH LTC3545EUD#PBF LTC3545IUD#PBF LTC3545EUD-1#PBF LTC3545IUD-1#PBF TAPE AND REEL LTC3545EUD#TRPBF LTC3545IUD#TRPBF LTC3545EUD-1#TRPBF LTC3545IUD-1#TRPBF PART MARKING* LCSR LCSR LDDP LDDP PACKAGE DESCRIPTION 16-Lead (3mm x 3mm) Plastic QFN 16-Lead (3mm x 3mm) Plastic QFN 16-Lead (3mm x 3mm) Plastic QFN 16-Lead (3mm x 3mm) Plastic QFN TEMPERATURE RANGE -40C to 125C -40C to 125C -40C to 125C -40C to 125C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
SYMBOL VIN VFBx PARAMETER Input Voltage Range Regulated Feedback Voltage (Note 5) General Characteristics
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = PVIN = 3.6V unless otherwise noted. (Note 2)
CONDITIONS
MIN 2.25 0.592 0.588 0.588
TYP
MAX 5.5
UNITS V V V V %/V
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TA = 25C 0C TA 85C LTC3545IUD; -40C < TA < 125C VIN = 2.25V to 5.5V

0.6 0.6 0.6 0.08
0.608 0.612 0.612 0.15
VFBx
Reference Voltage Line Regulation (Note 5)
2
LTC3545/LTC3545-1 ELECTRICAL CHARACTERISTICS
SYMBOL VLOADREG IFBx IS PARAMETER Output Voltage Load Regulation (Notes 5, 6) Feedback Pin Leakage (Note 5) Input DC Bias Current (All Regulators Enabled) Pulse Skip (Active Mode) Burst Mode Operation (All Regulators Sleeping) Shutdown (RUNX = 0V) Oscillator Frequency Synchronization Frequency RUNx Input High Voltage RUNx Input Low Voltage RUN Leakage Current SWx Leakage SYNC Leakage Power Good Threshold-Deviation From VFB Steady State (0.6V) Power Good Pull-Down On-Resistance VRUNx = 0V, VSWx = 0V or 5.5V, VIN = 5.5V VRUN = 0V, VSYNC = 0V or 5.5V, VIN = 5.5V VFBx Ramping Up VFBx Ramping Down IPGD = 50mA
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = PVIN = 3.6V unless otherwise noted. (Note 3)
CONDITIONS MIN TYP 0.5 80 ILOAD = 0A, 2.25MHz VFBx = 0.5V VFBx = 0.7V
MAX
UNITS % nA A A A MHz MHz V V A A A % %
680 58 0.1 1.8 1 1 2.25

750 70 2.0 2.7 3 0.3
fOSC fSYNC VRUN(HIGH) VRUN(LOW) IRUNx ILSWx ISYNC TPGOODx RPGOODx
LTC3545 Only
0.1 0.1 0.1 -7.5 -10 14 0.93 VFBx = 10% to 90% Fullscale 1 ILOAD = 0A, 2.25MHz VFBx = 0.5V VFBx = 0.7V ISWx = 100mA ISWx = -100mA (High VCC to Low)
1 1 1
50
V
MODE/SYNC Thresholds Individual Regulator Characteristics (One Regulator Enabled) tSS IPK IQ Soft-Start Period Peak Switch Current Limit Input DC Bias Current Pulse Skip (Active Mode) Burst Mode Operation (Sleeping) RDS(ON) of P-Channel FET (Note 7) RDS(ON) of N-Channel FET (Note 7) Undervoltage Lockout
850 1.3 310 31 0.35 0.35 1.8
1100 1.6
s A A A
RPFET RNFET VUVLO
2.25
V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3545E/LTC3545E-1 are guaranteed to meet performance specifications from 0C to 85C. Specifications over the -40C to 125C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3545I/LTC3545I-1 are guaranteed to meet performance specifications over the full -40C to 125C operating junction temperature range. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD)(68C/W) This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature
will exceed 125C when overtemperature is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 5: The LTC3545/LTC3545-1 are tested in a proprietary test mode that connects VFB to the output of the error amplifier. Note 6: Load regulation is inferred by measuring the regulation loop gain. Note 7: The QFN switch-on resistance is guaranteed by correlation to water level measurements. Note 8: Guaranteed by long-term current density limitations.
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LTC3545/LTC3545-1 TYPICAL PERFORMANCE CHARACTERISTICS
VREF vs Temperature at 2.25V, 3.6V, 5.5V
0.615 SWITCHING FREQUENCY (MHz) 0.610 0.605 VREF (V) 0.600 0.595 0.590 0.585 -50 2.25V 3.6V 5.5V 0 50 100 TEMPERATURE (C) 150
3545 G01 3545 G02 3545 G03
Switching Frequency vs Supply Voltage and Temperature
3.0 1.2 1.0 0.8 VOUT ERROR (%) 2.5 0.6 0.4 0.2 0 -0.2 -0.4 6
Load Regulation, All Channels
TA = 25C VIN = 3.6V UNTESTED CHANNELS OFF PULSE SKIP MODE CHANNEL 1 CHANNEL 2 CHANNEL 3
2.0 fOSC = -40C fOSC = 0C fOSC = 25C fOSC = 80C 2 3 4 5 SUPPLY VOLTAGE (V)
1.5
0
200
400 600 LOAD CURRENT (mA)
800
Burst Mode Operation
100
Efficiency vs Supply Voltage
VOUT = 2V TA = 25C CHANNEL 3, ALL OTHERS OFF fOSC = 2.25MHz ILOAD = 250mA 60 50 SUPPLY CURRENT (A) 40 30 20 10 80 0
Supply Current vs Temperature Burst Mode Operation
SW 2V/DIV VOUT 20mV/DIV IL 100mA/DIV EFFICIENCY (%)
95
90
85 VIN = 3.6V VOUT = 1.8V ILOAD = 50mA fOSC = 2.25MHz 1s/DIV
3545 G04
VFB3 = 0.625V ILOAD = 0mA CHANNEL 3 ONLY -50 0
VIN = 5.5V VIN = 4.5V VIN = 3.5V VIN = 2.5V 150
3545 G06
2
3
4 SUPPLY VOLTAGE (V)
5
6
3545 G05
50 100 TEMPERATURE (C)
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LTC3545/LTC3545-1 TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Temperature, Pulse Skipping
450 400 SUPPLY CURRENT (A) 350 300 250 200 VFB3 = 0.625V ILOAD = 0mA CHANNEL 3 ONLY 0 VIN = 5.5V VIN = 4.5V VIN = 3.5V VIN = 2.5V 150
3545 G07 3545 G08 3545 G09
Efficiency vs Load Current, Burst Mode Operation
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 VIN = 2.7V VIN = 3.6V VIN = 4.2V TA = 25C VOUT = 1.8V CHANNEL 3, OTHER CHANNELS OFF fOSC = 2.25MHz 1 10 100 LOAD CURRENT (mA) 1000 EFFICIENCY (%) 100 90 80 70 60 50 40 30 20 10
Efficiency vs Load Current, Pulse Skipping Operation
VIN = 2.7V VIN = 3.6V VIN = 4.2V TA = 25C VOUT = 1.8V CHANNEL 3, OTHER CHANNELS OFF fOSC = 2.25MHz 1 10 100 LOAD CURRENT (mA) 1000
150 -50
50 100 TEMPERATURE (C)
0 0.1
0 0.1
Channel 1 Load Step Response
Channel 2 Load Step Response
Channel 3 Load Step Response
VOUT1 100mV/DIV IL 500mA/DIV ILOAD 500mA/DIV
3545 G10
VOUT2 100mV/DIV IL 500mA/DIV ILOAD 500mA/DIV
3545 G11
VOUT3 100mV/DIV IL 500mA/DIV ILOAD 500mA/DIV
3545 G12
TA = 25C 10s/DIV VIN = 3.6V VOUT = 1.2V LOAD STEP 0mA TO 600mA Burst Mode OPERATION
TA = 25C 10s/DIV VIN = 3.6V VOUT = 1.5V LOAD STEP 0mA TO 600mA Burst Mode OPERATION
10s/DIV TA = 25C VIN = 3.6V VOUT = 1.8V LOAD STEP 0mA TO 600mA Burst Mode OPERATION
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LTC3545/LTC3545-1 TYPICAL PERFORMANCE CHARACTERISTICS
Start-Up From Shutdown Loaded Start-Up From Shutdown No Load
VOUT2 2mV/DIV VOUT1 VOUT2 VOUT3 (ALL 1V/DIV) RUNX 5V/DIV ISUPPLY 1A/DIV TA = 25C 200s/DIV VIN = 3.6V ILOAD = 600mA, ALL CHANNELS
3545 G13
Load Step Crosstalk
VOUT1 1V/DIV VOUT2 1V/DIV VOUT3 1V/DIV ISUPPLY 50mA/DIV 200s/DIV TA = 25C VIN = 3.6V ILOAD = 0, ALL CHANNELS
3545 G14
VOUT3 2mV/DIV VOUT1 100mV/DIV ILOAD CH1 50mA/DIV
3545 G15
TA = 25C 200s/DIV VIN = 3.6V 500mA LOAD STEP IN CHANNEL1 CHANNELS 2 AND 3 LOADED AT 400mA EACH
PFET RDS(ON) vs Supply Voltage
0.60 0.50 0.40 RDS(ON) () RDS(ON) () 0.30 0.20 0.10 0 2 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 6
3545 G16
PFET RDS(ON) vs Temperature
TA = 125C TA = 80C TA = 25C TA = 0C TA = -40C 4 3 5 SUPPLY VOLTAGE (V)
0 -40
VIN = 2.5V VIN = 3.5V VIN = 5.5V 10 60 TEMPERATURE (C) 110
3545 G17
NFET RDS(ON) vs Supply Voltage
0.60 0.50 0.40 RDS(ON) () RDS(ON) () 0.30 0.20 0.10 0 2 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 6
3545 G18
NFET RDS(ON) vs Temperature
TA = 125C TA = 80C TA = 25C TA = 0C TA = -40C 4 3 5 SUPPLY VOLTAGE (V)
0 -40
VIN = 2.5V VIN = 3.5V VIN = 5.5V 10 60 TEMPERATURE (C) 110
3545 G19
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LTC3545/LTC3545-1 PIN FUNCTIONS
SW1 (Pin 1): Switch Node Connection to Inductor for Regulator 1. This pin connects to the internal power MOSFET switches. PGOOD1 (Pin 2): This open-drain output voltage is pulled to a logic low when VFB1 is below 0.54V (VOUT1 is below 90% of regulated level). RUN2 (Pin 3): Regulator 2 Enable Pin. Apply a voltage greater than VRUN(HIGH) to enable this regulator. PGOOD2 (Pin 4): This open-drain output voltage is pulled to a logic low when VFB2 is below 0.54V (VOUT2 is below 90% of regulated level). SW2 (Pin 5): Switch Node Connection to Inductor for Regulator 2. This pin connects to the internal power MOSFET switches. PGND (Pin 6): Regulators 2 and 3 Power Path Return. PVIN (Pin 7): Power Path Supply Pin for Regulators 2 and 3. This pin must be closely decoupled to PGND, with a 4.7F or greater ceramic capacitor. SW3 (Pin 8): Switch Node Connection to Inductor for Regulator 3. This pin connects to the internal power MOSFET switches. SYNC/MODE (Pin 9, LTC3545 Only): Mode Select and External Clock Input. When pulled low, part operates in Burst Mode operation. When pulled high, part operates in pulse skipping mode. When driven by a 1MHz to 3MHz external clock, the part operates in pulse skipping mode with a switching frequency equal to the external clock. PGOOD3 (Pin 9, LTC3545-1 Only): This open-drain output voltage is pulled to a logic low when VFB3 is below 0.54V (VOUT3 is below 90% of regulated level). The LTC3545-1 operates in Burst Mode operation only. RUN3 (Pin 10): Regulator 3 Enable Pin. Apply a voltage greater than VRUN(HIGH) to enable this regulator. VFB3 (Pin 11): Regulator 3 Feedback Pin. This pin receives the feedback voltage from an external resistive divider across the output. VFB2 (Pin 12): Regulator 2 Feedback Pin. This pin receives the feedback voltage from an external resistive divider across the output. VFB1 (Pin 13): Regulator 1 Feedback Pin. This pin receives the feedback voltage from an external resistive divider across the output. RUN1 (Pin 14): Regulator 1 Enable Pin. Apply a voltage greater than VRUN(HIGH) to enable this regulator. VIN (Pin 15): Supply Pin for Internal Reference and Control Circuitry. Power path supply for regulator 1. GNDA (Pin 16): Ground Pin for Internal Reference and Control Circuitry. Power path return for regulator 1. Exposed Pad (Pin 17): GND. Must be soldered to the PCB.
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LTC3545/LTC3545-1 FUNCTIONAL DIAGRAMS
RUN3 RUN2 VIN GNDA SYNC/MODE (LTC3545 ONLY) RUN1
SHDN 0.6V REF RUN LOGIC OSC
PGOOD3 (LTC3545-1 ONLY) IBIAS3 SW3 VFB3 REG3 POWER
PGOOD1 IBIAS100 POWER SW1 VFB1 REG1
PGOOD2 IBIAS2 SW2 VFB2 REG2 PVIN PGND
3545 FD01
POWER
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LTC3545/LTC3545-1 FUNCTIONAL DIAGRAMS
PGOOD REGULATOR BURST CLAMP + - 0.6V SLOPE COMP PVIN
+
VFBX 50mV
-
EA 0.6V
-
ITH VSLEEP SLEEP
-
ICOMP
+
10
+
+
BURST S RS LATCH Q
SOFT-START
R
Q SWITCHING LOGIC AND BLANKING CIRCUIT
ANTI SHOOTTHRU
SWX
IRCMP SHUTDOWN
0.6V VREF
OSC OSC
-
3545 FD02
+
PGND
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LTC3545/LTC3545-1 OPERATION
MAIN CONTROL LOOP The LTC3545/LTC3545-1 use a constant frequency, current mode step-down architecture. Both the main (P-channel MOSFET) and synchronous (N-channel MOSFET) switches are internal. During normal operation, the internal top power MOSFET is turned on each cycle when the oscillator sets the RS latch, and turned off when the current comparator, ICOMP , resets the RS latch. The peak inductor current at which ICOMP resets the RS latch, is controlled by the output of error amplifier EA. When the load current increases, it causes a slight decrease in the feedback voltage FB relative to the 0.6V reference, which in turn, causes the EA amplifier's output voltage to increase until the average inductor current matches the new load current. While the top MOSFET is off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by the current reversal comparator, IRCMP , or the beginning of the next clock cycle. PULSE SKIPPING/Burst Mode OPERATION At light loads, the inductor current may reach zero or reverse on each pulse. The bottom MOSFET is turned off by the current reversal comparator, IRCMP , and the switch voltage will ring. This is discontinuous mode operation, and is normal behavior for the switching regulator. At very light loads, the LTC3545/LTC3545-1 will automatically begin operating in either pulse skipping or Burst Mode operation depending on the state of the MODE/SYNC pin (LTC3545). In either case the part will begin to skip cycles in order to maintain regulation. In pulse skip mode, the current pulses are smaller and more frequent, giving lower output ripple. In this mode, internal circuitry remains on and the pulses occur more frequently resulting in lower efficiency than in Burst Mode operation at light loads. In Burst Mode operation, the part supplies fewer, larger current pulses, resulting in higher output ripple, but much higher light load efficiency than pulse skip mode. Efficiency is also improved by turning off much of the internal circuitry during the dead time between pulses.
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LTC3545/LTC3545-1 OPERATION
SOFT-START Soft-start reduces surge currents on VIN and output overshoot during start-up. Soft-start on the LTC3545/ LTC3545-1 is implemented by internally ramping the reference signal fed to the error amplifier over approximately a 1ms period. Figure 1 shows the behavior of the regulator channels during start-up. Short-Circuit Protection Short-circuit protection is achieved by monitoring the inductor current. When the current exceeds a predetermined level, the main switch is turned off, and the synchronous switch is turned on long enough to allow the current in the inductor to decay below the fault threshold. This prevents a catastrophic inductor current run-away condition, but will still provide current to the output. Output voltage regulation in this condition is not achieved. DROPOUT OPERATION As the input supply voltage decreases to a value approaching the output voltage, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage
200s/DIV TA = 25C VIN = 3.6V ILOAD = 0mA, ALL CHANNELS
forces the main switch to remain on for more than one cycle until it reaches 100% duty cycle. The output voltage will then be determined by the input voltage minus the voltage drop across the P-channel MOSFET and the inductor. An important detail to remember is that at low input supply voltages, the RDS(ON) of the P-channel switch increases (see Typical Performance Characteristics). Therefore, the user should calculate the power dissipation when the LTC3545/LTC3545-1 is used at 100% duty cycle with low input voltage (See Thermal Considerations in the Applications Information section).
VOUT1 VOUT2 VOUT3 (ALL 1V/DIV) RUNX 2V/DIV
3545 F01
Figure 1. Start-Up from Shutdown, No Load
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LTC3545/LTC3545-1 APPLICATIONS INFORMATION
The basic LTC3545/LTC3545-1 application circuit is shown on the first page of this data sheet. External component selection is driven by the load requirement and begins with the selection of L followed by CIN and COUT. Inductor Selection For most applications, the value of the inductor will fall in the range of 1H to 10H. Its value is chosen based on the desired ripple current. Large inductor values lower ripple current and small inductor values result in higher ripple currents. Higher VIN or VOUT also increases the ripple current as shown in Equation 1. A reasonable starting point for setting ripple current for an 800mA regulator is IL = 320mA (40% of 800mA). V IL = VOUT 1 - OUT VIN ( )(L ) 1 (1)
Table 1. Representative Surface Mount Inductors
PART NUMBER Wurth WETPC 744031 CoilCraft LPS4012 VALUE (H) 1.5 2.5 3.6 1 1.5 2.2 3.3 1.4 2.4 3.6 1.5 2.2 3.3 DCR ( MAX) 0.035 0.045 0.065 0.06 0.07 0.1 0.1 0.055 0.094 0.13 0.043 0.075 0.11 MAX DC CURRENT (A) 1.75 1.45 1.38 2.5 2.5 2.1 1.5 1.8 1.3 1.1 1.55 1.2 1.1 W x L x H (mm3) 3.8 x 3.8 x 1.65
4.0 x 4.0 x 1.1
Sumida CDH38D11/ SLD Sumida CDRH3D16
4.0 x 4.0 x 1.2
3.8 x 3.8 x 1.8
CIN and COUT Selection In continuous mode, a worst-case estimate for the input current ripple can be determined by assuming that the source current of the top MOSFET is a square wave of duty cycle VOUT/VIN, and amplitude IOUT(MAX). To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: IRMS IOUT(MAX ) VOUT ( VIN - VOUT ) VIN
The DC current rating of the inductor should be at least equal to the maximum load current plus half the ripple current to prevent core saturation. Thus, a 960mA rated inductor should be enough for most applications (800mA + 160mA). For better efficiency, choose a low DCR inductor. Inductor Core Selection Different core materials and shapes will change the size/current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don't radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. The choice of which style inductor to use often depends more on the price vs size requirements and any radiated field/EMI requirements than on what the LTC3545/LTC3545-1 require to operate. Table 1 shows typical surface mount inductors that work well in LTC3545/LTC3545-1 applications.
This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design. Note that the capacitor manufacturer's ripple current ratings are often based on 2000 hours of life (non-ceramic capacitors). This makes it advisable to further de-rate the capacitor, or choose a capacitor rated at a higher temperature than required. Always consult the manufacturer if there is any question.
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LTC3545/LTC3545-1 APPLICATIONS INFORMATION
The selection of COUT is driven by the required effective series resistance (ESR). Typically, once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. The output ripple VOUT is determined by: 1 VOUT IL ESR + 8 * * COUT where f = operating frequency, COUT = output capacitance and IL = ripple current in the inductor. For a fixed output voltage, the output ripple is highest at maximum input voltage since IL increases with input voltage. Using Ceramic Input and Output Capacitors Higher value, lower cost, ceramic capacitors are now widely available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. Because the LTC3545/LTC3545-1's control loop does not depend on the output capacitor's ESR for stable operation, ceramic capacitors can be used freely to achieve very low output ripple and small circuit size. However, care must be taken when ceramic capacitors are used at the input and the output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN, large enough to damage the part. When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. Output Voltage Programming The output voltage is set by tying VFB to a resistive divider according to the following formula: R2 VOUT = 0.6 V 1+ R1 The external resistive divider is connected to the output allowing remote voltage sensing as shown in Figure 2.
0.6V VOUT 5.5V R2 VFB LTC3545 GND
3545 F02
R1
Figure 2. Setting the LTC3545 Output Voltage
Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses in LTC3545/LTC3545-1 circuits: VIN quiescent current and I2R losses. VIN quiescent current loss dominates the efficiency loss at low load currents, whereas the I2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of little consequence as illustrated on the front page of the data sheet.
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LTC3545/LTC3545-1 APPLICATIONS INFORMATION
1. The quiescent current is due to two components: the DC bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge, dQ, moves from PVIN to ground. The resulting dQ/dt is the current out of PVIN that is typically larger than the DC bias current and proportional to frequency. Both the DC bias and gate charge losses are proportional to PVIN and thus their effects will be more pronounced at higher supply voltages. 2. I2R losses are calculated from the resistances of the internal switches, RSW, and external inductor RL. In continuous mode, the average output current flowing through inductor L is "chopped" between the main switch and the synchronous switch. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 - DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current. Other losses when in switching operation, including CIN and COUT ESR dissipative losses and inductor core losses, generally account for less than 2% total additional loss. Thermal Considerations The LTC3545/LTC3545-1 requires the package backplane metal to be well soldered to the PC board. This gives the QFN package exceptional thermal properties, making it difficult in normal operation to exceed the maximum junction temperature of the part. In most applications the LTC3545/LTC3545-1 do not dissipate much heat due to their high efficiency. In applications where the LTC3545/ LTC3545-1 are running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part if it is not well thermally grounded. If the junction temperature reaches approximately 150C, the power switches will be turned off and the SW nodes will become high impedance. To prevent the LTC3545/LTC3545-1 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TR = PD * JA where PD is the power dissipated by the regulator and JA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: TJ = TA + TR where TA is the ambient temperature. As an example, consider one channel of the LTC3545/ LTC3545-1 in dropout at an input voltage of 2.5V, a load current of 800mA, and an ambient temperature of 85C. From the typical performance graph of switch resistance, the RDS(ON) of the P-channel switch at 85C can be estimated as 0.42. Therefore, power dissipated by the channel is: PD = ILOAD2 * RDS(ON) = 0.27W The JA for the 3mm x 3mm QFN package is 68C/W. The temperature rise due to this power dissipation is: TR = JA * PD = 18C And a junction temperature of: TJ = 85C + 18C = 103C which is below the maximum junction temperature of 125C. This would not be the case if all three channels were operating at 800mA in dropout. Then TR = 55C, limiting the allowed ambient temperature in this scenario to less than 70C.
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14
LTC3545/LTC3545-1 APPLICATIONS INFORMATION
Similar situations can occur when all three channels are operating at maximum loads at high ambient temperature. As an example, consider a channel supplying 800mA at 1.8V output and 85% efficiency. The dissipated power can be calculated using 1- E Loss = PO = 1.4W * 0.17 = 0.25W E where PO is the output power and E is the efficiency. In this case the temperature rise is 17C, similar to the dropout scenario described above. Whereas one channel operating at these levels will safely fall within the temperature limitations of the part, three channels operating simultaneously at these levels will place limits on the peak ambient temperature. Note that at higher supply voltages, the junction temperature is lower due to reduced switch resistance RDS(ON). Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to (ILOAD * ESR), where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT, which generates a feedback error signal. The regulator loop then acts to return VOUT to its steady-state value. During this recovery time VOUT can be monitored for overshoot or ringing that would indicate a stability problem. For a detailed explanation of switching control loop theory, see Application Note 76. A second, more severe transient is caused by switching in loads with large (>1F) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25 * CLOAD). Thus, a 10F capacitor charging to 3.3V would require a 250s rise time, limiting the charging current to about 130mA. Design Example As a design example, consider using the LTC3545/LTC35451 in a portable application with a Li-Ion battery. The battery provides VIN ranging from 2.8V to 4.2V. The demand on one channel at 2.5V is 600mA. Using this channel as an example, first calculate the inductor value for 40% ripple current (240mA in this example) at maximum VIN. Using a form of Equation 1: L1= 2.5V 2.5V 1- = 1.41H (2.25MHz )(240mA ) 3.6V
Use the closest standard value of 1.5H. For low ripple applications, 10F is a good choice for the output capacitor. A smaller output capacitor will shorten transient response settling time, but also increase the load transient ripple. A value for C5 = 4.7F should suffice as the source impedance of a Li-Ion battery is very low. C5 and C1 both provide switching current to the output power switches. They should be placed as close a possible to the chip between VIN/GNDA and PVIN/PGND respectively. PVIN and PGND are the supply and return power paths for both channels 2 and 3, so a value of 10F for C1 is appropriate. The feedback resistors program the output voltage. Minimizing the current in these resistors will maximize efficiency at very light loads, but totals on the order of 200k are a good compromise between efficiency and immunity to any adverse effects of PCB parasitic capacitance on the feedback pins. Choosing 10A as the feedback current with 0.6V feedback voltage makes R4 = 60k. A close standard 1% resistor is 60.4k. Using: 2.5V R3 = - 1 * R4 = 191.1k 0.6 V The closest standard 1% resistor is 191k. A 20pF feedforward capacitor is recommended to improve transient response. The component values for the other channels are chosen in a similar fashion. Figure 4 shows the complete schematic for this example, along with the efficiency curve and burst mode ripple at an output current for the 2.5V output.
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15
LTC3545/LTC3545-1 APPLICATIONS INFORMATION
PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3545/LTC3545-1. These items are also illustrated graphically in Figures 3 and 4. Figure 3 shows the power path components and traces. In this figure the feedback networks are not shown since they reside on the bottom side of the board. Check the following in your layout: 1. The power traces consisting of the PGND trace, the SW trace, the PVIN trace, the VIN and GNDA traces, should be kept short direct and wide. 2. Does each of the VFBx pins connect directly to the respective feedback resistors? The resistive dividers must be connected between the (+) plate of the corresponding output filter capacitor (e.g. C2) and GNDA. If the circuit being powered is at such a distance from the part where voltage drops along circuit traces are large, consider a Kelvin connection from the powered circuit back to the resistive dividers. 3. Keep C1 and C5 as close to the part as possible. 4. Keep the switching nodes (SWx) away from the sensitive VFBx nodes. 5. Keep the ground connected plates of the input and output capacitors as close as possible. 6. Care should be taken to provide enough space between unshielded inductors in order to minimize any transformer coupling.
VOUT3 L3 C4 (VIA TO FEEDBACK NETWORK)
SW3 VIN C1 C5 GNDA SW1 SW2 C3 C2 L1 L2 VOUT2
3545 F03
PVIN
PGND
(VIA TO FEEDBACK NETWORK)
(VIA TO FEEDBACK NETWORK)
VOUT1
Figure 3. Layout Diagram
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16
LTC3545/LTC3545-1 TYPICAL APPLICATIONS
L1 1.5H C6 20pF C5 4.7F 1 2 3 4 5 6 VIN 2.7V TO 5.5V 7 C1 10F 10V 8 SW1 PGOOD1 RUN2 PGOOD2 SW2 PGND PVIN SW3 LTC3545 GNDA VIN RUN1 VFB1 VFB2 VFB3 RUN3 SYNC/MODE GND 17 L3 1.5H C8 20pF R7 165k R8 110k
3545 TA02
R3 191k R4 60.4k
C2 10F 6.3V
E3 VOUT1 2.5V AT 0.8A E4 GND
R2 511k E2 PGOOD2 E1 PGOOD1
R1 511k
16 15 14 13 12 11 10 9 R6 100k C7 20pF R5 100k L2 1.5H C3 10F 6.3V E7 VOUT2 1.2V AT 0.8A E6 GND
C4 10F 6.3V
E5 VOUT3 1.5V AT 0.8A E8 GND
Overall Efficiency vs Channel 1 Load Current
100 90 OVERALL EFFICIENCY (%) 80 70 60 50 40 30 20 10 0 0.1 TA = 25C VIN = 3.6V VOUT = 2.5V fOSC = 2.25MHz CHANNEL 2 = 1.2V, ILOAD = 400mA CHANNEL 3 = 1.5V, ILOAD = 400mA 1 10 100 CHANNEL 1 LOAD CURRENT (mA) 1000
3545 TA03
Burst Mode Ripple
VOUT3 AC COUPLED 20mV/DIV IL3 250mA/DIV
SW3 2V/DIV
3545 TA04
TA = 25C VIN = 3.6V VOUT = 1.5V ILOAD = 50mA fOSC = 2.25MHz
1s/DIV
Figure 4. LTC3545 Low Ripple Burst Mode Operation
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17
LTC3545/LTC3545-1 TYPICAL APPLICATIONS
L1 1.5H C6 20pF C5 10F R3 100k R4 100k C2 10F E3 VOUT1 1.2V AT 0.8A E4 GND
R9 511k E9 PGOOD3 E2 PGOOD2
R2 511k E1 PGOOD1
R1 511k
1 2 3 4 5 6
SW1 PGOOD1 RUN2 PGOOD2 SW2 PGND PVIN SW3
LTC3545-1 GNDA VIN RUN1 VFB1 VFB2 VFB3 RUN3 PGOOD3 GND 17
16 15 14 13 12 11 10 9
L2 1.5H C7 20pF R5 165k R6 110k L3 1.5H C8 20pF R7 133k R8 66.5k
3545 TA05
C3 10F
E7 VOUT2 1.5V AT 0.8A E6 GND
VIN 2.5V TO 5.5V
7 C1 4.7F 8
C4 10F
E5 VOUT3 1.8V AT 0.8A E8 GND
3-Channel Power Sequencing
RUN1
VOUT1 VOUT2 VOUT3 PGOOD3
TA = 25C VIN = 3.6V
400s/DIV
3545 TA06
Figure 5. LTC3545-1 Three PGOODs and Power Sequencing
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18
LTC3545/LTC3545-1 PACKAGE DESCRIPTION
UD Package 16-Lead Plastic QFN (3mm 3mm)
(Reference LTC DWG # 05-08-1700 Rev A)
Exposed Pad Variation AA
0.70 0.05
3.50
0.05 2.10
1.65 0.05 0.05 (4 SIDES)
PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.75 0.05 BOTTOM VIEW--EXPOSED PAD R = 0.115 TYP 15 16 0.40 1 1.65 0.10 (4-SIDES) 2 0.10 PIN 1 NOTCH R = 0.20 TYP OR 0.25 45 CHAMFER
3.00 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6)
(UD16 VAR A) QFN 1207 REV A
0.200 REF 0.00 - 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-4) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25
0.05
0.50 BSC
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC3545/LTC3545-1 RELATED PARTS
PART NUMBER LTC3405/LTC3405A LTC3406/LTC3406B LTC3407/LTC3407-2 LTC3409 LTC3410/LTC3410B LTC3411 LTC3412 LTC3419 LTC3441/LTC3442 LTC3443 LTC3531/LTC3531-3 LTC3531-3.3 LTC3532 LTC3544/LTC3544B LTC3547 LTC3548/LTC3548-1 LTC3548-2 LTC3561 DESCRIPTION 300mA IOUT, 1.5MHz, Synchronous Step-Down DC/DC Converters 600mA IOUT, 1.5MHz, Synchronous Step-Down DC/DC Converters Dual 600mA/800mA IOUT, 1.5MHz/2.25MHz, Synchronous Step-Down DC/DC Converters 600mA IOUT, 1.7MHz/2.6MHz, Synchronous Step-Down DC/DC Converter 300mA IOUT, 2.25MHz, Synchronous Step-Down DC/DC Converters 1.25A IOUT, 4MHz, Synchronous Step-Down DC/DC Converter 2.5A IOUT, 4MHz, Synchronous Step-Down DC/DC Converter COMMENTS 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 20A, ISD < 1A, ThinSOTTM Package 96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 20A, ISD < 1A, ThinSOT Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40A, ISD < 1A, 10-Lead MSE, DFN Packages 96% Efficiency, VIN: 1.6V to 5.5V, VOUT(MIN) = 0.6V, IQ = 65A, ISD < 1A, DFN Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 26A, ISD < 1A, SC70 Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60A, ISD < 1A, 10-Lead MSE, DFN Packages 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60A, ISD < 1A, 16-Lead TSSOPE Package
Dual 600mA, 2.25MHz, Synchronous Step-Down DC/DC 96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 35A, ISD < 1A, MS10, 3mm x 3mm DFN Package Converter 1.2A IOUT, 2MHz, Synchronous Buck-Boost DC/DC Converters 200mA IOUT, 1.5MHz, Synchronous Buck-Boost DC/DC Converters 500mA IOUT, 2MHz, Synchronous Buck-Boost DC/DC Converter 300mA, 2 x 200mA, 100mA, 2.25MHz Quad Synchronous Step-Down DC/DC Converter Dual 300mA IOUT, 2.25MHz, Synchronous Step-Down DC/DC Converter Dual 400mA/800mA IOUT, 2.25MHz, Synchronous Step-Down DC/DC Converters 1.25A IOUT, 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.4V to 5.5V, VOUT(MIN): 2.4V to 5.25V, IQ = 50A, ISD < 1A, DFN Package 95% Efficiency, VIN: 1.8V to 5.5V, VOUT(MIN): 2V to 5V, IQ = 16A, ISD < 1A, ThinSOT, DFN Packages 95% Efficiency, VIN: 2.4V to 5.5V, VOUT(MIN): 2.4V to 5.25V, IQ = 35A, ISD < 1A, 10-Lead MSE, DFN Packages 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60A, ISD < 1A, 3mm x 3mm QFN Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40A, ISD < 1A, 8-Lead DFN Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40A, ISD < 1A, 10-Lead MSE, DFN Packages 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 240A, ISD < 1A, DFN Package
ThinSOT is a Trademark of Linear Technology Corporation.
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20 Linear Technology Corporation
(408) 432-1900
LT 0908 REV B * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
FAX: (408) 434-0507 www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2008

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